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2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
The M5M5Y816 is a f amily of low v oltage 8-Mbit static RAMs organized as 524288-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18m CMOS technology . The M5M5Y816 is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5Y816WG is packaged in a CSP (chip scale package), with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards. Version, Operating temperature Part name -
FEATURES
Single 1.65~2.3V power supply Small stand-by current: 0.5A (2.0V, ty p.) No clocks, No ref resh Data retention supply v oltage =1.3V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.18m CMOS Package: 48ball 7.5mm x 8.5mm CSP
Power Supply
Access time
max.
70ns
Activ e current Icc1 25C 40C 25C 40C 70C 85C (2.3V, max) Stand-by c urrent (A) Ratings (max.) * Ty pical
30mA (10MHz) 3mA (1MHz)
I-version
-40 ~ +85C
M5M5Y816WG -70HI 1.65 ~ 2.3V M5M5Y816WG -85HI 1.65 ~ 2.3V
0.5 85ns
1
2
4
15
30
* Typical parameter indicates the value for the center of distribution at 2.0V, and not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1 A B C D E F G H
BC1
2
OE
3
A0
4
A1
5
A2
6
S2
Pin
DQ16 BC2 A3 A4 S1 DQ1
Function Address input Chip select input 1 Chip select input 2 Write control input Output enable input Lower By te (DQ1 ~ 8) Upper By te (DQ9 ~ 16) Power supply Ground supply
A0 ~ A18 S1 S2 W OE BC1 BC2 Vcc GND
DQ14
DQ15
A5
A6
DQ2
DQ3
DQ1 ~ DQ16 Data input / output
GND
DQ13
A17
NCor GND*
A7
DQ4
VCC
VCC
DQ12
A16
DQ5
GND
DQ11
DQ10
A14
A15
DQ7
DQ6
DQ9
N.C.
A12
A13
W
DQ8
A18
A8
A9
A10
A11
N.C.
Outline: 48F7Q NC: No Connection *Don't connect E3 ball to v oltage lev el more than 0V
MITSUBISHI ELECTRIC
1
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
FUNCTION
The M5M5Y816WG is organized as 524288-words by 16-bit. These dev ices operate on a single +1.65~2.3V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of t he dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A18) must be set up bef ore the write cycle and must be stable during the entire cy c le. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by te are in a selectable mode in which both reading and writing are enabled, and lowerby t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lower-by te are in a selectable mode and upperby t e are in a non-selectable mode.
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply current is reduced as low as 0.5A(25C, ty pical), and the memory data can be held at +1.3V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 H L H X L L L L L L L L L S2 BC1 BC2 LXX LXX HXX XHH HL H HL H HL H HH L HHL HH L HL L HL L HL L W OE XX XX XX XX LX HL HH L X HL HH LX HL HH Mode
Non selection Non selection Non selection Non selection
DQ1~8
DQ9~16
Write Read Write Read Write Read
BLOCK DIAGRAM
A0 A1 MEMORY ARRAY 524288 WORDS x 16 BITS A17 A18 S1 S2 BC1 BC2 W
CLOCK GENERATOR
High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z
High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z
Icc Standby Standby Standby Standby Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e
DQ 1
DQ 8
-
DQ 9
DQ 16
Vcc
GND OE
MITSUBISHI ELECTRIC
2
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C I-v ersion Ratings Units
Vcc VI VO Pd Ta T stg
-0.5* ~ +2.7 -0.2* ~ Vcc + 0.2 (max. 2.7V) 0 ~ Vcc 700 - 40 ~ +85 - 65 ~ +150
V mW
C C
* -0.7V in case of AC (Pulse width < 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=1.65~ 2.3V, unless otherwise noted) Limits Min 0.7 x Vcc Ty p Max Vcc+0.2 Units
Parameter High-lev el input v oltage Low-lev el input v oltage
High-level output voltage
Conditions
VIH VIL VOH VOL II IO
Low-lev el output v oltage Input leakage current Output leakage current ( AC,MOS lev el )
IOH= -0.1mA IOL=0.1mA VI =0 ~ Vcc
BC1 and BC2=VIH or S1=VIH or S2=VIL or OE=VIH, VI/O=0 ~ Vcc < BC1 and BC2< 0.2V, S1= 0.2V, S2 Vcc-0.2V = > other inputs < 0.2V or = Vcc-0.2V = Output - open (duty 100%)
-0.2 * 1.3
0.4 0.2 1 1 30 3 30 3 2 4 15 30 0.5
V
A
Icc1 Activ e supply c urrent
f = 10MHz f = 1MHz f = 10MHz f = 1MHz ~ +25C ~ +40C ~ +70C ~ +85C
Activ e supply c urrent Icc2 ( AC,TTL lev el )
BC1 and BC2=VIL , S1=V IL ,S2=V IH other pins =V IH or VIL Output - open (duty 100%)
> (1) S1 = Vcc - 0.2V, > S2 = Vcc - 0.2V, other inputs = 0 ~ Vcc (2) S2 < 0.2V, = other inputs = 0 ~ Vcc > (3) BC1 and BC2 = Vcc - 0.2V > S1 < 0.2V, S2= Vcc - 0.2V = other inputs = 0 ~ Vcc
-
20 1.5 20 1.5 0.5 1 -
mA
Icc3 Stand by s upply current
( AC,MOS lev el )
A
Icc4 Stand by s upply current ( AC,TTL lev el )
BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc
mA
* -0.7V in case of AC (Pulse width < 30ns) =
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical parameter indicates the value for the center of distribution at 2.0V, and not 100% tested.
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions
(Vcc=1.65 ~ 2.3V, unless otherwise noted) Limits Ty p Units
Min
Max
CI CO
VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz
10 10
pF
MITSUBISHI ELECTRIC
3
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply v oltage
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=1.65 ~ 2.3V, unless otherwise noted)
1.65~2.3V Input pulse VIH=0.7 x Vcc+0.2V, VIL=0.2V Input rise time and f all time 5ns
Ref erence lev el Output loads
DQ CL
1TTL
VOH=VOL=0.9V
Transition is measured 200mV from steady state voltage.(for ten,tdis)
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Including scope and jig capacitance
(2) READ CYCLE
Symbol tCR Parameter Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address
Fig.1 Output load
Limits
70HI
Min 70 Max 70 70 70 70 70 35 25 25 25 25 25 10 10 10 10 5 10 10 10 10 10 5 10
85HI
Min 85 Max 85 85 85 85 85 45 30 30 30 30 30
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis (S1) tdis (S2) tdis (BC1) tdis (BC2) tdis (OE) ten(S1) ten(S2) ten(BC1) ten(BC2) ten(OE) tV(A)
(3) WRITE CYCLE
Limits Symbol Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low
70HI
Min 70 55 0 65 65 65 65 65 30 0 0 Max
85HI
Min 85 60 0 70 70 70 70 70 35 0 0 Max
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten(W) ten(OE)
25 25 5 5 5 5
30 30
MITSUBISHI ELECTRIC
4
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
(4)TIMING DIAGRAMS Read cycle
A0~18 ta(A) ta(BC1) or ta(BC2) BC1,BC2
(Note3)
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM tCR
tv (A)
tdis (BC1) or tdis (BC1) ta(S1)
(Note3)
S1
(Note3)
tdis (S1) ta(S2)
(Note3)
S2
(Note3)
tdis (S2) ta (OE)
(Note3)
OE
(Note3) W = "H" lev el
ten (OE) ten (BC1) ten (BC2) ten (S1) ten (S2) tCW
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W control mode )
A0~18
tsu (BC1) or tsu(BC2) BC1,BC2
(Note3) (Note3)
S1
(Note3)
tsu (S1)
(Note3)
S2
(Note3)
tsu (S2)
(Note3)
OE tsu (A) W tdis(OE) DQ1~16
tsu (A-WH) tw (W) tdis (W)
trec (W) ten(OE) ten (W)
DATA IN STABLE
tsu (D)
th (D) 5
MITSUBISHI ELECTRIC
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
A0~18 tsu (A) BC1,BC2 S1
(Note3)
tCW
tsu (BC1) or tsu (BC2)
trec (W)
(Note3)
S2
(Note3) (Note5) (Note4) (Note3) (Note3) (Note3)
W
tsu (D) DQ1~16
DATA IN STABLE
th (D)
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
6
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Write cycle (S1 control mode)
A0~18
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCW
BC1,BC2
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Write cycle (S2 control mode)
A0~18
tCW
BC1,BC2
(Note3)
tsu (A)
tsu (S2)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
MITSUBISHI ELECTRIC
7
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Vcc Parameter Test conditions Min
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Limits Ty p
Max
Units V V V
(PD) Power down supply voltage Byte control input BC1 & BC2
1.3
1.65V Vcc(PD) 1.3V Vcc(PD) 1.65V
VI (BC)
0.7xVcc Vcc(PD) 0.7xVcc Vcc(PD) ~ +25C ~ +40C ~ +70C ~ +85C
VI (S1) VI (S2)
1.65V Vcc(PD) Chip select input S1 Chip select input S2 Vcc=1.3V
> (1) S1 = Vcc - 0.2V,
1.3V
Vcc(PD) 1.65V
-
0.1 0.2 -
0.2 1.5 3 10 20
V
Icc
(PD)
Power down supply c urrent
other inputs = 0 ~ Vcc (2) S2 < 0.2V, = other inputs = 0 ~ Vcc > (3) BC1 and BC2 = Vcc - 0.2V > S1 < 0.2V, S2= Vcc - 0.2V = other inputs = 0 ~ Vcc
A
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recov ery t ime
Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 1.3V, and not 100% tested.
Limits Test conditions Min Ty p Max
Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC control mode Vcc tsu (PD) 0.7 x Vcc BC1 BC2 S1 control mode Vcc tsu (PD) 0.7 x Vcc S1 S2 control mode Vcc S2 tsu (PD) 0.2V 0.2V S2 0.2V S1 > Vcc-0.2V = 1.65V 1.65V trec (PD) 0.7 x Vcc BC1 , BC2> Vcc-0.2V = 1.65V 1.65V trec (PD) 0.7 x Vcc
1.65V
1.65V
trec (PD)
MITSUBISHI ELECTRIC
8
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Keep safety first in your circuit designs!
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products betterand more reliable, but there isalways the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
9
2001.05.22
Ver. 0.1
MITSUBISHI LSIs
Preliminary
M5M5Y816WG -70HI, -85HI
Revision History
Notice: This is not a final specification. Some parametric limits are subject to change.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Ver. 0.0 / May.07.2001 Ver. 0.1 / May.22.2001
Initial Change of package name 48FJA ---> 48F7Q
MITSUBISHI ELECTRIC
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